(a) Field of the Invention
The present invention relates to a technique of manufacturing a wiring board for use in mounting of a chip component such as a semiconductor device, and more particularly to a method of manufacturing a multilayer wiring board (also called a “semiconductor package”) having a multilayer structure adapted to achieve high density and high performance.
(b) Description of the Related Art
Heretofore, a build-up process has been widely used as a technique of manufacturing a multilayer wiring board. The use of the build-up process enables the fabrication of a variety of multilayer wiring boards by using combinations of materials (typified by resins) for an interlayer dielectric and via hole formation processes. A typical manufacturing process of the build-up process involves stacking up layers on both sides (top and bottom sides) of a core substrate serving as a base member by repeating in turn the formation of resin layers (insulating layers) on both sides of the substrate, the formation of via holes in the resin layers, and the formation of conductive patterns (wiring layers) on the resin layers and also in the via holes.
As the art related to such multilayer wiring board formation, for example, Japanese unexamined Patent Publication (JPP) 2001-15922 discloses the following technique. In this technique, a conductive bump is caused to pass through an uncured insulating material substrate (prepreg) by pressing, against the prepreg, a conductor layer provided with the conductive bump. Here, the conductive bump is substantially conically molded from a resin containing an electrically conductive material such as metal powder dispersed therein. The insulating material substrate is made of a sheet of a thermosetting resin such as epoxy resin. Thereby, the conductive bump ensures electrical conduction in a thickness direction of the insulating material substrate.
As described above, a typical wiring formation technique using the conventional build-up process has a disadvantage of requiring a considerable time due to adopting the approach of stacking the resin layers (having the via holes formed therein) and the conductor layers alternately one on top of another, starting from the inside (or the core substrate side). In particular, this technique poses a problem of requiring a longer time period for manufacturing a larger number of stacked layers. This is because the larger the number of stacked layers, the greater the amount of needed workloads.
Moreover, since a multilayer wiring structure is manufactured through a formation process in which layers are formed one by one, the yield of the formation process is the sum of yields throughout all steps in the formation process. For example, where a defective condition is encountered at any one of the steps or at every step, a multilayer wiring board obtained as a final product is judged as a “defective,” the shipment of which is not permitted. In other words, the approach, such as the build-up process, of stacking up the layers one by one in sequence has a problem of causing a reduction in the yield of the product (the multilayer wiring board).
In addition, a great difference in thermal expansion coefficient exists between a constituent material for the conductor layer, such as copper (Cu), and a constituent material for the resin layer, such as epoxy resin. Accordingly, the adoption of the approach of stacking up the conductor layers and the resin layers alternately at given time intervals poses a problem in that “warpage” may occur because thermal stress depending on the difference in the thermal expansion coefficient may be generated in the thickness direction of the layers at interfaces between the conductor layers and the resin layers during the stacking-up process.